Dr Jaume Abella
Co-Founder, CEO, and CTO
PhD on Computer Architecture from the Polytechnic University of Catalonia (2005)
More than 20 years of experience in multicore design, validation and verification,
timing analysis and functional safety
Dr Francisco J. Cazorla
Co-Founder and senior fellow
PhD on Computer Architecture from the Polytechnic University of Catalonia (2005)
More than 20 years of experience in multi-threaded processors
(simultaneous mulit-threading, multicores, etc.)
Dr Enrico Mezzetti
Senior fellow
PhD on Timing Analysis from
University of Bologna and Padua (2011)
More than 10 years of experience in real-time systems, RTOS, WCET and schedulability analyses
Mikel Fernandez
Senior Engineer
MSc in Computer Architecture, Systems, and Networks
from the Universitat Politècnica de Catalunya (2010).
More than 10 years of experience in multicore embedded systems, RTOS, simulation, and performance analysis.
Josep Jorba
Senior Engineer
MSc in Telecommunication
from the Universitat Politècnica de Catalunya (2003).
More than 15 years of experience in embedded systems, real-time operating systems and certification processes including building automation, industrial communications and automotive domains.
Dr Alejandro Serrano
Embedded HW Architect
PhD on Computer Architecture from
University of Alicante
Consolidated expertise on on hardware reliability with focus on timing analysis solutions for embedded multicore time-critical systems
Juan M. Reina, MSc
Embedded SW Engineer
MSc in Electronic Systems for Smart Environments
from the Universidad de Málaga.
Consolidated experience in the design and development
of profiling solutions for embedded MPSoCs
