Challenges in hardware analysis of complex MPSoCs
An insightful understanding of the hardware platform is a fundamental prerequisite of any timing analysis approach. Multicore COTS platforms are increasingly assessed and deployed as reference computing solution in several embedded critical domains, with avionics and automotive being the clearest example of such trend. The complexity of the considered computing solutions, while necessary to sustain performance-hungry software functionalities, is making hardware analysis an overwhelmingly difficult, and often unaffordably onerous, task.
Current MPSoCs integrate IP from different vendors. The hardware integrator and the IP vendors provide technical reference manuals (TRM) whose overall size can be in the order of dozens of thousands of pages.
Maspatechnologies experts, who have 40+ years of combined experience in computer architecture, help distilling the information from the TRMs to identify those pieces of information related to the timing behavior.
Hardware expertise covers the following essential elements for supporting multicore timing analysis:
- Critical Configuration Settings (CCS) Analysis
- Interference Channels (IC) Analysis
- Hardware Event Monitor Analysis and Validation
Critical Configuration Settings (CCS)
CCS plays a key role in determining how hardware resources are shared. Hence, the selection of specific settings for the platform play a critical role in determining the system behavior. CCS analysis is explicitly required in CAST-32A to capture and assess the impact of hardware/software configuration on multicore timing interference. In fact, CSS are a powerful means to mitigate the impact of contention on timing behavior.
Maspatechnologies experts can assist in CCS analysis and configuration:
- Identification of CCS
- Assessment of customer specific CCS settings, as determined by the BSP/OS provider
- Guidance for CCS selection and preliminary platform exploration
Interference Channels (ICH)
Maspatechnologies tools and analysis services help you identifying the potential sources of multicore timing interference in the platform of interest. Our technology allows understanding, for potentially different CCS settings, how sensitive is your application to multicore contention, what are the most conflictive ICH for your application, and how to mitigate them. ICH analysis is carried out in a two-step process, starting from an analysis of available TRMs, followed by an empirical characterization of the ICHs building on Maspatechnologies’ micro-benchmarks.
Services related to ICH analysis include:
- Identification and classification of ICHs for the specific target and CCS configuration
- Selection of micro-benchmarks to be deployed for the empirical characterization of ICHs
- Support for the elaboration of certification arguments
Hardware Event Monitor Analysis (HEMs)
At the core of the verification artifacts for a successful Multicore Timing Analysis are performance monitoring counters (PMCs) to validate micro-benchmarks and usage of ICHs. PMCs are used to read hardware event monitors (HEMs), and are part of the overall performance monitoring unit (Debug Support Unit). Maspatechnologies provides a set of technologies to validate HEMs, PMCs, the performance monitoring unit (PMU), and the software library used to configure PMCs. In particular we provide:
- Assessment of HEM/PMC/PMU support: we have detected cases in which HEMs do not behave according to the TRMs, with significant side-effects on timing validation. Maspatechnologies provides a mechanism to assess the correctness of the HEMs, PMCs and the elements of the PMU infrastructure related to event counting.
- Assessment of HEM software infrastructure: regardless of whether you exploit an in-band or out-of-band reading of the hardware event monitors, your solution can be subject to inaccuracies. Maspatechnologies helps you assessing any deviation introduced by your HEM-reading approach.