Support evidence for Multicore Certification
- We design and deploy platform-specific micro-benchmarks to confirm, identify, and assess the potential sources of multicore timing interference (Interference Channels identification)
- Test designs are formulated and executed to produce trustworthy evidence on the worst-case impact of multicore interference on the execution time of target applications, under specific hardware and software configurations
- Microbenchmark technology provides the necessary evidence upon which to build a certification argument on the absence or tight control of the potential sources of timing interference, as required by CAST-32A and ISO 26262
«Does the MPSoC provide robust resource partitioning and robust time partitioning?» «Does the ARINC 653 real-time operating system provide time and space partitioning? Is this enough to meet CAST-32A resource partitioning goals?» «Do hardware providers produce a complete description of interference channels (ICH) and critical configuration settings (CCS)?» «Can I fully control ICHs via proper CCS configurations?» These are just few of the questions emanating from the reference guideline CAST-32A and DO-178C. Maspatechnologies offers consultancy services to help you answering all these questions for your target MCP and RTOS, as necessary steps for a successful certification process. We have performed interference channel analysis, robust partitioning analysis, critical configuration setting analysis for many avionics relevant architectures. Maspatechnologies’ Microbenchmark technology is pivotal to achieve CAST-32A objectives. Micro-benchmarks can be used to:
- Compare MCP platforms.
- Show evidence on the mitigation applied to control the impact on interference channels.
- Develop evidence to support your certification application.
Micro-benchmarks are certifiable and follow a DO-178C inspired development process.
Maspatechnologies tools and services can be leveraged to support ISO 26262 verification and qualification strategies. Micro-benchmark based solutions and tools allow for performance optimization, adherence to freedom from interference, and robustness testing. Micro-benchmarks enable the deployment of structured test-based verification strategies for the assessment of timing budgets in multicore scenarios in the scope of SOTIF regulation. Maspatechnologies also offers specialized services in the area of multicore time interference, including tailored services for customer processes. Services include but are not limited to the following:
- Task Contention Models (TCMs): analytical model aiming at bounding the timing interference of multiple software deployment scenarios and consolidation alternatives. The model can be used within a deployment configuration optimization process to maximize utilization and limit overruns.
- MPSoC timing characterization services to allow a fast evaluation of alternative target platforms and select the right multicore device.
- Stress and robustness testing for SEooC as well as for specific integrations with Microbenchmark and surrogate applications technologies.
Verification and Validation of micro-benchmarks
The design and development of micro-benchmarks follows the classic V-model software development life-cycle, with strong focus on design and verification and validation activities (V&V). Micro-benchmarks undergo a rigorous verification and validation campaign to guarantee they are triggering the expected behavior on the underlying platform, and ultimately producing the expected effects on the execution of applications. For each micro-benchmark, formal verification artifacts are produced (verification requirements, test design, and respective traceability matrix) to support full traceability between micro-benchmark requirements and test results, and make the micro-benchmark certifiable. Verification artifacts are provided to end users as an input to their specific certification project.