Multicore Performance and Timing Analysis
Services & Technologies
Hardware Analysis Services
For a wide variety of multicore processors and accelerators we identify and characterize the main critical configuration settings (CCS), interference channels (ICH), and available hardware event monitors (HEMs); all pillars of a successful multicore certification process. Our technology provides means for performance testing and freedom from interference assessment.
Specifically designed code snippets that put a configurable load on the desired ICHs to validate a wide variety of timing requirements, from isolation properties to the maximum contention on an ICH.
Multicore contention modeling
Obtain fast estimates of multicore contention (interference) impact on co-running tasks’ execution time. Highly recommended in early design stages to explore different task/process to core mapping and data-code to memory mapping.
Specialized micro-benchmarks that stress the ICHs as a reference application does. Help tightening WCET estimates by adjusting the load on the ICHs to the actual expected load, and ease robustness testing tailoring micro-benchmark characteristics.
Target industrial domains
The increased performance needs of automotive applications can only be met with the processing power brought by heterogeneous MultiProcessors Systems on Chip (MPSoCs). MPSoC usage, however, confronts with the challenges stemming from holistic performance optimizations of multiple applications, and the need to provide evidence for safety requirements adherence, including freedom from interference.
Identifying and setting right values for the critical configuration settings; identifying and quantifying interference channels; providing evidence of the correctness of hardware event monitors (performance monitoring counters); are all key traits to show adherence to CAST-32A.